专利名称：Low consumption linear voltage regulator
with high supply line rejection
发明人：Capici, Salvatore Vincenzo,Milazzo,
Patrizia,Pulvirenti, Francesco
申请号：EP97830434.3申请日：19970829公开号：EP0899643A1公开日：19990303
专利附图：
摘要：A linear type of voltage regulator, having an input terminal (VBAT) adapted toreceive a supply voltage thereon, and an output terminal (VOUT) adapted to deliver a
regulated output voltage, comprises a power transistor (M1) and a driving circuittherefor; the driving circuit basically comprises an operational amplifier (OP) having adifferential input stage biased by a bias current (Iop) which varies proportionally with theoutput current (Iload) of the regulator.
申请人：STMicroelectronics S.r.l.
地址：Via C. Olivetti, 2 20041 Agrate Brianza (Milano) IT
国籍：IT
代理机构：Botti, Mario
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