HCF4021B
ASYNCHRONOUS PARALLEL IN OR SYNCHRONOUS
SERIAL IN/SERIAL OUT 8 - STAGE STATIC SHIFT REGISTER
s
ss
s
ss
ss
MEDIUM SPEED OPERATION : 12 MHz (Typ.) CLOCK RATE AT VDD - VSS = 10VFULLY STATIC OPERATION
8 MASTER-SLAVE FLIP-FLOPS PLUS OUTPUT BUFFERING AND CONTROL GATING
QUIESCENT CURRENT SPECIFIED UP TO 20V
5V, 10V AND 15V PARAMETRIC RATINGSINPUT LEAKAGE CURRENT
II = 100nA (MAX) AT VDD = 18V TA = 25°C100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B \" STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES\"
DIPSOPORDER CODES
PACKAGEDIPSOP
TUBEHCF4021BEYHCF4021BM1
T & RHCF4021M013TR
DESCRIPTION
The HCF4021B is a monolithic integrated circuitfabricated in Metal Oxide Semiconductortechnology available in DIP and SOP packages. This device is an 8-stage parallel or serial input/serial output register having common CLOCK andPARALLEL/SERIAL CONTROL inputs, a singleSERIAL data input, and individual parallel \"JAM\"inputs to each register stage. Each register stageis a D-type, master-slave flip-flop in addition to anoutput from stage 8, \"Q\" outputs are also availablefrom stages 6 and 7. Serial entry is synchronouswith the clock but parallel entry is asynchronous.PIN CONNECTIONIn this device, entry is controlled by thePARALLEL/SERIAL CONTROL input. When thePARALLEL/SERIAL CONTROL input is low, datais serially shifted into the 8-stage registersynchronously with the positive transition of heclock line. When the PARALLEL/SERIALCONTROL input is high, data is jammed into the8-stage register via the parallel input lines andsynchronous with the positive transition of theclock line, the CLOCK input of the internal stage is\"forced\" when asynchronous parallel entry ismade. Register expansion using multiple packageis permitted.
September 20011/11
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HCF4021B
IINPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No7, 6, 5, 4, 13, 14, 15, 111
9102, 3, 12816
SYMBOLPI1 to PI8SERIAL INPARALLEL/SERIAL CONTROLCLOCKQ6, Q7, Q8
VSS
VDD
NAME AND FUNCTIONParallel InputSerial Input
Parallel/Serial Input Con-trol
Clock Input
Buffered OutputsNegative Supply VoltagePositive Supply Voltage
TRUTH TABLE
CLOCKXXXXSERIAL INPUTXXXX01XX : Don’t CarePARALLEL/SERIAL CONTROL111100XPI - 10011XXXPI - n0101XXXQ1 (INTERNAL)001101Q1Qn0101Qn - 1Qn - 1QnLOGIC DIAGRAM
2/11
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HCF4021B
ABSOLUTE MAXIMUM RATINGS
SymbolVDDVIIIPDTopTstg
Supply VoltageDC Input VoltageDC Input Current
Power Dissipation per Package
Power Dissipation per Output TransistorOperating TemperatureStorage Temperature
Parameter
Value-0.5 to +22-0.5 to VDD + 0.5
± 10200100-55 to +125-65 to +150
UnitVVmAmWmW°C°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.
All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
SymbolVDDVITop
Supply VoltageInput Voltage
Operating Temperature
Parameter
Value3 to 200 to VDD-55 to 125
UnitVV°C
3/11
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HCF4021B
DC SPECIFICATIONS
Test Condition
Symbol
Parameter
VI(V)0/50/100/150/200/50/100/155/010/015/0
0.5/4.51/91.5/13.54.5/0.59/113.5/1.52.54.69.513.50.40.51.5VO(V)
|IO|VDD(µA)(V)
5101520510155101551015510155510155101518
TA = 25°CMin.
Typ.0.040.040.040.08
4.959.9514.95
0.050.050.053.5711
1.534
-1.36-0.44-1.1-3.00.441.13.0
-3.2-1-2.6-6.812.66.8±10-55
±0.17.5
-1.1-0.36-0.9-2.40.360.92.4
±1
3.5711
1.534
-1.1-0.36-0.9-2.40.360.92.4
±1
Max.51020100
4.959.9514.95
0.050.050.05
3.5711
1.534
Value-40 to 85°CMin.
Max.1503006003000
4.959.9514.95
0.050.050.05
-55 to 125°CMin.
Max.1503006003000
Unit
IL
Quiescent Current
µA
VOH
High Level Output Voltage
Low Level Output Voltage
High Level Input VoltageLow Level Input VoltageOutput Drive Current
VOL
VIH
VIL
IOH
IOL
Output Sink Current
Input Leakage Current
Input Capacitance
0/50/50/100/150/50/100/150/18
<1<1<1<1<1<1<1<1<1<1<1<1<1<1<1<1<1<1<1
V
V
V
V
mA
mAµApF
IICI
Any InputAny Input
The Noise Margin for both \"1\" and \"0\" level is: 1V min. with VDD=5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
4/11
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HCF4021B
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)
Test Condition
Symbol
Parameter
VDD (V)51015510155101551015510155101551015510155101551015
Min.
Value (*)Typ.1608060100504061217904025
Max.32016012020010080
Unit
CLOCKED OPERATION
tPLH tPHLPropagation Delay Time
ns
tTHL tTLHTransition Time
ns
fCL (1)
Maximum Clock Input FrequencyClock Pulse Width
tW
368.51808050
MHz
ns
151515
tr , tf
Clock Input Rise or Fall Time
Setup Time, serial Input (ref to CL)
Setup Time, Parallel Inputs (ref to P/S)
Hold Time, serial in,
parallel in, parallel /serial control
P/S Pulse Widht
µs
tsetup
tsetup
thold
tWH
trem
P/S Removal Time (ref to CL)
12080605030200001608050280140100
604030251510
ns
ns
ns
8040251407050
ns
ns
(*) Typical temperature coefficient for all VDD value is 0.3 %/°C.
(1) If more than one unit is cascaded trCL should be made less than or equal to the sum of the transition time and the fixed propagation delay of the output of the driving stage of the estimated capacitive load.
5/11
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HCF4021B
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance)RL = 200KΩ
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1 : PROPAGATION DELAY TIMES, CLOCK PULSE WIDTH (f=1MHz; 50% duty cycle)
6/11
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HCF4021B
WAVEFORM 2 : SETUP AND HOLD TIMES (SI TO CLOCK) (f=1MHz; 50% duty cycle)
WAVEFORM 3 : SETUP AND HOLD TIME (PI TO P/S) (f=1MHz; 50% duty cycle)
7/11
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HCF4021B
WAVEFORM 4 : PULSE WIDTH AND REMOVAL TIME (P/S TO CLOCK) (f=1MHz; 50% duty cycle)
8/11
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HCF4021BPlastic DIP-16 (0.25) MECHANICAL DATAmm.DIM.MIN.a1Bbb1DEee3FILZ3.31.278.52.5417.787.15.10.1300.0500.510.770.50.25200.3350.1000.7000.2800.2011.65TYPMAX.MIN.0.0200.0300.0200.0100.7870.065TYP.MAX.inchP001C9/11元器件交易网www.cecb2b.com
HCF4021BSO-16 MECHANICAL DATADIM.Aa1a2bb1Cc1DEee3FGLMS3.84.60.50.350.190.545° (typ.) 9.8100.3855.81.278.894.05.31.270.628°(max.)0.1490.1810.0196.20.2280.0500.3500.1570.2080.0500.0240.1mm.MIN.TYPMAX.1.750.21.650.460.250.0130.0070.0190.003MIN.inchTYP.MAX.0.0680.0070.0640.0180.0100.3930.244PO13H10/11元器件交易网www.cecb2b.com
HCF4021B
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