BDR6122T
1.8A Low-Voltage H-Bridge Driver
DESCRIPTION
The BDR6122T provides an integrated motor driver for cameras, consumer products, toys and other application with low-voltage or battery-powered motion control.
FEATURE
H-Bridge Motor Driver
- DC Motor or Other Loads
- Low On-Resistance : HS+LS 280mΩ 1.8-A Maximum DC Drive Current Separate Motor and Logic Supply - Motor VM : 0 to 11V - Logic VCC : 1.8V to 5V Low-Power Sleep Mode - 10nA with IVM and IVCC Small Package and Footprint
- 8-Pin DFN with Thermal PAD (2.0 X 2.0 mm) - 8-Pin SOP
Protection Features
- VCC Under-voltage Lockout - Over-Current Protection - Thermal Shutdown
The BDR6122T can supply up to 1.8A of output DC current. It operates on a motor power supply (VM) from 0 to 11V and a device power supply voltage (VCC) of 1.8V to 5V.
Ultra- low rds-on allows SOP-8 package available. The BDR6122T has a PWM (IN1-IN2) input interface
Full protections are integrated with over-current protection, under-voltage lockout and over-temperature shutdown.
APPLICATION
Cameras
DSLR Lenses
Consumer Products Toys Robotics
BLOCK DIAGRAM
VM(0V to 11V)VMVCC(1.8V to 5V)VCCIN1VMGate DriverUVLOLogicOCPOUT1VMMIN2Gate DrivernSLEEPOCPOUT2OverTempGNDFigure 1. Function Block Diagram
BDR6122T
APPLICATION CIRCUIT
VMVCC*C30.1uFC1123VMOUT1ThermalPadVCCnSLEEPIN1IN280.1uF7C2M4OUT2GND65Figure 2. Schematic of Application
*C3 is optional for better performance. Details are referred to at the chapter “Power Supply Recommendations”.
V1.0
2 2017
BDR6122T
ORDER INFORMATION Valid Part Number BDR6122T-S BDR6122T
Package Type 8-Pin, SOP, 150 MIL 8-Pin, DFN Top Code BDR6122T-S BDR6122T PIN DESCRIPTION
DFN-8SOP-8VM187ThermalPadVCCnSLEEPIN1IN2VM18765VCCnSLEEPIN1IN2OUT1OUT2GND234OUT1OUT2GND23465
Pin Name VM OUT1 OUT2 GND IN2 IN1 nSLEEP VCC I/O POWER OUTPUT OUTPUT POWER INPUT INPUT INPUT POWER Description Motor power supply Motor output 1 Motor output 2 Ground Input 2 Input 1 Sleep mode input Logic power supply Pin No. 1 2 3 4 5 6 7 8
V1.0
3 2017
BDR6122T
FUNCTION DESCRIPTION
BRIDGE CONTROL
The BDR6122T is controlled using a PWM input interface, also called an IN-IN interface. Each output is controlled by a corresponding input pin. nSLEEP IN1 IN2 OUT1 OUT2 Function (DC Motor) 0 1 1 1 1 X 0 0 1 1 X 0 1 0 1 Z Z L H L Z Z H L L Coast Coast Reverse Forward Brake Table 1. Control Logic
PROTECTION MANAGEMENT
The BDR6122T is fully protected against VCC under-voltage, overcurrent, and over-temperature events. Fault Condition H-Bridge Recovery VCC under-voltage Over-current Thermal shutdown VCC < 1.7V IOUT > 1.9A (MIN) TJ > 150℃ (MIN) Disable Disable VCC>1.8V tRETRY TJ < 150℃ Disable Table 2. Fault Behavior
FUNCTIONAL MODES
The BDR6122T is active unless the nSLEEP pin is brought logic low. In sleep mode, the H-bridge FETs are disabled Hi-Z. The BDR6122T is brought out of sleep mode automatically if nSLEEP is brought logic high. Mode Condition H-Bridge Operating Sleep mode nSLEEP pin=1 nSLEEP pin=0 Operating Disabled Disabled Fault encountered Any fault condition met Table 3. Operation Modes
V1.0
4 2017
BDR6122T
POWER SUPPLY RECOMMENDATIONS
Having appropriate local bulk capacitance is an important factor in motor-drive system design. It is generally beneficial to have more bulk capacitance.
The amount of local bulk capacitor needed depends on the following factors , The highest current required by the motor system.
The power-supply capacitance and ability to source current
The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple
The type of motor used (brushed dc, brushless dc, stepper) The motor braking method
The inductance between the power supply and motor drive system limits the rate at which current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied.
The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to supply. Parasitic WireInductancePower SupplyMotor Driver SystemVMMotorDriverGNDLocal Bulk CapacitorIC BypassCapacitor Figure 3. Motor Driver System with External Power Supply
PCB LAYOUT
The VM and VCC should be bypassed to GND using low-ESR ceramic capacitors with recommended value of 0.1µF. These capacitors should be placed as close to the VM and VCC as possible with a thick trace or ground plane connection to GND.
0.1uF0.1uFVM18765VCCnSLEEPIN1IN2OUT1OUT2GND234Figure 4. Simplified Layout Example
V1.0
5
2017
BDR6122T
ABSOLUTE MAXIMUM RATINGS Parameters Motor power supply voltage , VM Logic power supply voltage , VCC Operating Temperature, Top Storage Temperature, Tstg Operation Humidity Storage Humidity HBM ESD All Pins MM CDM* *CDM test is based on ANSI/ESDA/JECEC JS-002-2014
Min -0.3 -0.3 -40 -40 20 20 ±4 ±0.4 ±1.5 Max 12 5.5 150 150 85 90 Unit V V °C °C % % KV KV KV RECOMMENDED OPERATING CONDITIONS VM VCC IOUT fPWM VLOGIC TA Parameters Motor power supply voltage Logic power supply voltage Motor peak current Externally applied PWM frequency Logic level input voltage Operating ambient temperature Min 0 1.8 0 0 0 -40 Max 11 5 1.8 250 5 85 Unit V V A KHz V °C
V1.0
6 2017
BDR6122T
ELECTRICALCHARACTERISTICS
TA=25℃ , over recommended operating conditions unless otherwise noted Symbol Parameter Test Conditions Power Supplies(VM,VCC) VM Current VM=5V ; VCC=3V; No PWM VM coast current IVM1 Coast Mode VM=5V ; VCC=3V ; No PWM VM F/R current IVM2 Forward/Reverse Mode VM=5V ; VCC=3V ; No PWM VM brake current IVM3 Brake Mode VM=5V ; VCC=3V VM PWM current IVM4 PWM=50KHz VM sleep current VM=5V ; VCC=3V nSLEEP=0 IVMQ VCC Current IVCC1 IVCC2 IVCC3 IVCC4 VCC coast current VCC F/R current VCC brake current VCC PWM current VM=5V ; VCC=3V ; No PWM Coast Mode VM=5V ; VCC=3V ; No PWM Forward/Reverse Mode VM=5V ; VCC=3V ; No PWM Brake Mode VM=5V ; VCC=3V PWM=50KHz VM=5V ; VCC=3V nSLEEP=0 VIN=0V VIN=3.3V IN1 IN2 nSLEEP VM=5V ; VCC=3V ; Io=800mA ; Tj=25℃ VOUT=0V 380 450 480 450 2 100 280 5 1 160 500 650 650 650 0.3*VCC 5 50 1.7 3.5 µA µA µA µA nA V V µA µA KΩ mΩ nA V V A mS ℃ Min Typ Max Unit 65 300 65 240 5 90 500 90 400 µA µA µA µA nA VCC sleep current IVCCQ Control Inputs (IN1, IN2, nSLEEP) Input logic low voltage VIL Input logic high voltage VIH Input logic low current IIL Input logic high current IIH Pull down resistance RPD Motor Driver Outputs (OUT1, OUT2) rDS(ON) HS + LS FETs on-resistance 0.5*VCC 1.8 1.9 Off-state leakage current IOFF Protection Circuits VUVLO IOCP tRETRY TTSD VCC under-voltage lockout VCC falling VCC rising Over-current protection trip level Over-current retry time Thermal shutdown temperature Die temperature
V1.0
7 2017
BDR6122T
TIMING REQUIREMENTS
TA=25℃, VM=5V, VCC=3V, RL=20Ω Time Parameter t1 Output enable time t2 t3 t4 t5 t6 twake Output disable time Delay time, INx high to OUTx high Delay time, INx low to OUTx low Output rise time Output fall time Wake time , nSLEEP rising edge to part active Max 0.8 0.8 0.7 0.7 0.5 0.5 5 Unit µS µS µS µS µS µS µS IN1IN2t1OUT1Zt3ZZOUT2t4t2Z80%20%t580%20%t6OUTxFigure 5. Input and Output Timing
V1.0
8 2017
BDR6122T
TYPICAL OPERATING CHARACTERISTICS
(VM=5V, VCC=3V unless otherwise noted) VM Sleep Current (nA)1086420-40-20020406080Ambient Temperature (℃) Figure 6. IVMQ vs TA VCC Sleep Current (nA)126543210-40-200 20406080Ambient Temperature (℃) Figure 7. IVCCQ vs TA VM Operating Current (mA)VCC Operating Current (mA)0.30.250.20.150.10.050-40-20020406080Ambient Temperature (℃) Figure 8. IVM vs TA(50KHz PWM) 400HS + LS rds(ON)(mΩ)HS + LS rDS(ON)(mΩ)350300250200-40-20020406080Ambient Temperature (℃) Figure 10. HS + LS rDS-on vs TA 0.60.50.40.30.20.10-40-200 20406080Ambient Temperature (℃) 400350300250200 Figure 9. IVCC vs TA(50KHz PWM) VCC=2VVCC=3VVCC=5V 01234567VM (V)89101112 Figure 11. HS + LS rDS-on vs VM V1.0
9
2017
BDR6122T
Figure 12. 50% Duty Cycle , Forward Direction Figure 13. 20% Duty Cycle , Forward Direction Figure 14. 50% Duty Cycle , Reverse Direction Figure 15. 20% Duty Cycle , Reverse Direction
V1.0
10
2017
BDR6122T
PACKAGE INFORMATION
8-PIN, DFN
Symbol A A1 A3 b D E e D2 E2 L Note:Refer to JEDEC MO-229
Dimensions Nom. 0.75 0.02 0.20 REF 0.25 2.00 BSC 2.00 BSC 0.50 BSC 1.60 0.90 0.30 Max. 0.80 0.05 0.30 Min. 0.70 0 0.18 1.50 0.80 0.25 1.65 0.95 0.35
V1.0
11 2017
BDR6122T
8 PINS, SOP, 150MIL
Symbol A A1 A2 b c D E E1 e L Notes:
1. Refer to JEDEC MS-012AA 2. All dimensions are in millimeter
Min. - 0.10 1.25 0.31 0.10 0.40 0 Millimeter Nom. - - - - - 4.90 BSC 6.00 BSC 3.90 BSC 1.27BSC - -
Max. 1.75 0.25 - 0.51 0.25 1.27 8
V1.0
12 2017
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